`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2023/12/20 14:07:34
// Design Name: 
// Module Name: DMEM
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module DMEM(
    input clk,
    input ena,
    input write,
    input read,

    input [10:0] addr,
    input [31:0] in,
    output [31:0] out
);

reg [31:0] memory [0:31];
always@(posedge clk)
begin
    if(ena)begin
       if(write)
        memory[addr] <= in; 
    end
end
assign out  = (read && ena)? memory[addr] : 32'bz;
endmodule
